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FEATURES
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Low phase noise (-130 dBc @ 10kHz offset at 30MHz). CMOS output with OE tri-state control. Selectable oscillator "on" or "off" feature in output disable mode Ultra Low current consumption (<2.5mA, <2mA, <1.3mA at 27MHz respectively for PLL600-10, PLL600-20, and PLL600-30) Ultra Low disable mode current (<2uA when disabled with osc. off) 10 to 52MHz fundamental crystal input. Selectable divider by 2 (PLL600-10 only). 12mA drive capability at TTL output. Low jitter (RMS): 2.5ps period jitter. 2.25V to 3.63V DC operation. Available in die (fits 5x3.2 low profile substrate).
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Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
PAD LAYOUT
8 1 2 7 6 3 5 4
4U
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Preliminary
PLL600-10/-20/-30
SELECTION TABLE
SEL (PLL600-10)
DESCRIPTION
The PLL600-10/-20/-30 form a low cost family of XO dies, designed to consume the lowest current on the market for the 5MHz to 52MHz range. It accepts input crystal from 10 to 52MHz (fundamental resonant mode) and offers (PLL600-10 only) a selectable divider by 2 or no division. Providing less than 130dBc at 10kHz offset at 30MHz, and with a very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring low current frequency sources, such as handheld devices.
BLOCK DIAGRAM
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XIN
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t a
S a
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Internal Pull-up, default value is `1' when not connected. Selectable divider available on P600-10 only.
t e
0 1
U 4
0 1 0 1
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m o
DIVIDER
/2 No division
OE
OSCSEL
OUTPUT
0 0 1 1
Disabled Osc. Off Disabled Osc. On Enabled Enabled
Internal Pull-up, default value is `1' when not connected.
SEL
Reference Divider
CLK OE
XOUT
XTAL OSC
OSCSEL
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
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Rev 4/23/03 Page 1
Preliminary
PLL600-10/-20/-30
Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
PAD DESCRIPTION
Name
XOUT SEL GND OSCSEL CLK VDD OE XIN
Number
1 2 3 4 5 6 7 8
Type
I I P I O P I I Crystal output pin.
Description
PLL600-10 only: select pin. See Selection Table on page 1. PLL600-20/-30: no connect Output Enable input pin. Tri-states output if low. Enables output if high. Disable mode (on or off) select pin. See Selection Table on page 1. Output clock pin. +3.3V VDD power supply pin. Output Enable input pin. Tri-states output if low. Enables output if high. Crystal input pin.
See also pad coordinates table at the end of this document. SEL and OSCSEL have internal pull-ups, so the default value is `1' when not connected.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature Storage Temperature Ambient Operating Temperature* TS -65 -40
SYMBOL
V CC VI VO
MIN.
MAX.
7 V CC +0.5 V CC +0.5 260 150 85
UNITS
V V V C C C
-0.5 -0.5 -0.5
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/23/03 Page 2
Preliminary
PLL600-10/-20/-30
Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
2. AC Electrical Specifications PARAMETERS
Input Crystal Frequency At power-up (Vdd reaches 2.2V) Disable to enable, osc. Off Disbale to enable, osc. On Output Clock Rise/Fall Time VDD sensitivity Output Clock Duty Cycle Short Circuit Current
Note: (*) Preliminary Specifications still to be characterized.
CONDITIONS
MIN.
10
TYP.
MAX.
52
UNITS
MHz ms ms
10* 10* 500* 1.15 3.7 0.8 45 50 50 0.8 55
Settling time
s ns ppm % mA
0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load Frequency vs. VDD +/- 10% Measured @ 1.4V
3. Jitter and Phase Noise specification PARAMETERS
RMS Period Jitter (1 sigma - 1000 samples) Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier Phase Noise relative to carrier
CONDITIONS
with capacitive decoupling between VDD and GND. 30MHz @100Hz offset 30MHz @1kHz offset 30MHz @10kHz offset 30MHz @100kHz offset 30MHz @1MHz offset
MIN.
TYP.
2.1 -80 -110 -130 -138 -145
MAX.
2.5
UNITS
ps dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/23/03 Page 3
Preliminary
PLL600-10/-20/-30
Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
4. DC Specification PARAMETERS
Supply Current, Dynamic, with Loaded Outputs (at VDD = 3.3V) Respectively for PLL600 -10/-20/-30 IDD
SYMBOL
CONDITIONS
At 10MHz, Cload=15pF At 13.5MHz, Cload=15pF At 17.7MHz, Cload=15pF At 27MHz, Cload=15pF At 48MHz, Cload=15pF Output disabled, Osc. off Output disabled, Osc. On (PLL600-10) Output disabled, Osc. On (PLL600-20/-30)
MIN.
TYP.
1.3 / 1 / 0.75 1.5 / 1.2 / 0.8 1.8 / 1.5 / 1 2.4 / 2 / 1.2 4.1 / 3.5 / 2.1 2
MAX.
1.4 / 1.1 / 0.9 1.6 / 1.3 / 1 1.9 / 1.6 / 1.1 2.5 / 2.1 / 1.3 4.2 / 3.6 / 2.2 4 620 520
UNITS
mA
A A V V V
Supply Current in tristate Operating Voltage Output High Voltage Output Low Voltage Output High Voltage at CMOS level Output drive current Short Circuit Current ESD Protection
IDD
VDD VOH VOL VOHC IOH = -12mA* PLL600-30*, IOH = -12mA* ILO = 12mA* PLL600-30*, IOH = -12mA* IOH = -4mA At TTL level
2.25 2.4 2.4 2.9
3.63
0.4 0.32 VDD - 0.4 12 17 50 0.4
V V V mA mA
Human Body Model
3000
* Note: PLL600-30 has non-standard CMOS VOH and VOL levels for lower current consumption, but meet CMOS input stages needs. PLL600-30 should be used to drive pure capacitive loads only.
5. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Maximum Sustainable Drive Level Operating Drive Level C0 (for frequencies below 30MHz) C0 (for frequencies above 30MHz) ESR RS
Note: A detailed crystal specification document is also available for this part
SYMBOL
F XIN CL (xtal)
MIN.
10
TYP.
MAX.
52
UNITS
MHz pF
8.5 200 50 5 4 30
W W pF pF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/23/03 Page 4
Preliminary
PLL600-10/-20/-30
Ultra Low Current XO (Crystals from 10 MHz to 52 MHz)
PAD ASSIGNMENT
Pad # 1 2 3 4 5 6 7 8 Name XOUT SEL GND OSCSEL CLK VDD SEL XIN X (m) 94.183 94.157 94.183 94.193 715.472 715.307 715.472 476.906 Y (m) 768.599 605.029 331.756 140.379 203.866 455.726 626.716 888.881
Die dimensions and reference coordinates in m excluding scribe lines: Lower left: X=0, Y=0 Upper right: X=812, Y=986
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL600-XX D C
PART NUMBER TEMPERATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE D=Die
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/23/03 Page 5

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